AMD codenamed Bulldozer thread
An entirely new CPU design methodology. Let's hope it pays off like the Hammer. I get giddy just reading about it.

AMD's 2010 - 2011 Roadmaps: ~1B Transistor Llano APU, Bobcat and Bulldozer

AMD Unveils Bulldozer & Bobcat: 2011 Microachitectures

Too much info! *brain explodes*

lawl. But nice improvement.

i like the 2 int alu, better than intel stupid HT....too bad AMD cant have HT too....SMT is nice, but all in all...if AMD got HT + 2 int alu....i would love it (4 core, up to 8 core in 2 int, and another 8 from HT....im feeling giddy )

but...i just seen i9....50% improvement over i7....at 1K us $...............................

damn i want some super high end.....running oracle database is enough to make my comp crawl like a worm.....

XD then get your high end rig... =p

HT needs super smart scheduler to do its job properly. AMD's solution might be more efficient when the ALU units can be shared with one thread or have independent threads, I hope.

We can see the trend here. FP calculations will mostly be relegated to GPGPU while CPU will be more specialized at INT. Desktops, servers and HPC will benefit from this transition. Today, 64-bit FP code is already compiled under SIMD instructions (for GCC). CPU in the future might have small but efficient FPU for legacy code.